1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a device structure in which a parasitic transistor of an insulated gate bipolar transistor which comprises a trench MOS gate does not turn on easily so that a safe operating area (hereinafter "SOA") is large, and also relates to a method of manufacturing the same.
2. Description of the Background Art
FIG. 26 is a partial sectional view of a conventional insulated gate semiconductor device. As an example, an insulated gate bipolar transistor (hereinafter "IGBT"), in particular, an IGBT having a trench gate structure (and IGBT having a trench gate structure will be hereinafter referred to as a "U-type IGBT.") will be described.
In recent years, in a voltage oscillating circuit which serves as a high frequency invertor, a general use invertor, an AC servo, an air conditioner, etc., IGBTs have been very often used in various devices such as an intelligent power module which controls a variable speed of a tri-phase motor, to reduce energy consumption, the size and the weight of electric household appliances. While a switching characteristic, a saturation voltage and an SOA are in a trade-off relationship with each other in IGBTs, i.e., key devices in these various devices, IGBTs with a better switching characteristic, a low saturation voltage and a large SOA are demanded.
In FIG. 26, denoted at 1 is a P.sup.+ collector layer, denoted at 2 is an N.sup.- layer, denoted at 3 is a P base layer, denoted at 4 are N.sup.+ emitter regions, denoted at 5 are trenches, denoted at 6 are gate insulation films, denoted at 7 are gate electrodes, denoted at 8 is an interlayer insulation film, denoted at 9 is an N.sup.+ buffer layer, denoted at 10 is an emitter electrode, denoted at 11 is a collector electrode, and denoted at 12 are channel regions.
Now, an operation of an IGBT will be described.
When a predetermined collector voltage V.sub.CE is applied across the emitter electrode 10 and the collector electrode 11 and a predetermined gate voltage V.sub.GE is applied across the emitter electrode 10 and the gate electrodes 7, that is, when gates are turned on, the channel regions 12 are inverted into the N type, thereby creating channels. Through these channels, electrons are injected into the N.sup.- layer 2 from the emitter electrode 10. Injected electrons apply a forward bias across the P.sup.+ collector layer 1 and the N.sup.- layer 2 so that holes are injected into the N.sup.- layer 2 from the collector electrode 11 through the P.sup.+ collector layer 1 and the N.sup.+ buffer layer 9. The conductivity is changed consequently, and the resistance of the N.sup.- layer 2 is largely decreased to increase a current capacity of the IGBT. Collector-emitter voltage drop during this state (ON state) in the IGBT defines an ON-voltage (V.sub.CE (sat)).
To change the IGBT from an ON state into an OFF state, the gate voltage V.sub.GE applied across the emitter electrode 10 and the gate electrodes 7 is changed to 0 V or a reverse bias is applied across the emitter electrode 10 and the gate electrodes 7, thereby turning the gates off. As a result, the channel regions 12 inverted into the N type return to the P type so that injection of electrons from the emitter electrode 10 stops. Electrons and holes accumulated in the N.sup.- layer 2 then flow into the collector electrode 11 and the emitter electrode 10, respectively, or recombine with each other to perish.
The ON-voltage of the IGBT is primarily determined by a substantial resistance of the N.sup.- layer 2 which is necessary to hold a breakdown voltage. One of the factors which determines the substantial resistance is an ability of a MOSFET which forms the IGBT to supply electrons.
In a U-type IGBT in which narrow and deep grooves (trenches) are formed in a surface of a chip and MOSFETs are formed in side walls of the trenches, the ability of the MOSFETs to supply electrons is enhanced by reducing intervals between unit cells as much as possible.
In general, a cut-off current value under an applied high voltage is an important electric characteristic of an IGBT. It is therefore preferable to ensure as high a cut-off current value as possible. The better this electric characteristic is, the larger a reverse bias safe operating area (hereinafter "RBSOA") becomes.
Meanwhile, as can be clearly understood from FIG. 26 which shows the structure of the U-type IGBT, the U-type IGBT includes a parasitic bipolar transistor which is formed by the N.sup.+ emitter regions 4, the P base layer 3 and the N.sup.- layer 2.
When the parasitic bipolar transistor is turned on, the gate voltage V.sub.GE alone can not control a current which flows in the U-type IGBT any more, whereby the U-type IGBT is destroyed. Hence, as a measure to enlarge the RBSOA, various device structures have been proposed in which the cell size is small, using a trench gate structure so that the parasitic bipolar transistor does not easily turn on.
FIG. 27 is a partial sectional view showing an example of a conventional insulated gate semiconductor device which is described in Japanese Patent Unscreened Publication No. 60-253275.
In FIG. 27, denoted at 13 is a semiconductor substrate, denoted at 14 is a first major surface of the semiconductor substrate 13, and denoted at 15 are P.sup.+ regions. The other reference symbols are similar to those used in FIG. 24. The P.sup.+ regions 15 of the N.sup.+ emitter regions 4 are disposed simply to ensure a better contact with the emitter electrode 10. The impurity concentration of the P.sup.+ regions 15 is lower than that of the N.sup.+ emitter regions.
In this conventional insulated gate semiconductor device, when the same mask is used as a mask for forming the N.sup.+ emitter regions 4 and a mask for forming the V-shaped gate electrodes 7, alignment of masks becomes unnecessary and intervals between cells are reduced. However, since the gate electrodes 7 project from the first major surface 14 of the semiconductor substrate 13, to ensure the N.sup.+ emitter regions 4 contact the P.sup.+ regions 15 while allowing the interlayer insulation film 8 to be interposed across the emitter electrode 10 and the gate electrodes 7, the N.sup.+ emitter regions 4 must be formed large including an additional margin, when masks are aligned to each other during formation of the interlayer insulation film 8. This serves as an obstacle to an effort to reduce the intervals between the cells.
FIG. 28 is a schematic diagram showing a contact margin in the conventional technique.
In FIG. 28, the gate electrodes 7 are trench type electrodes rather than V-shaped electrodes. FIG. 28 shows additional areas which are necessary for the N.sup.+ emitter regions 4 to deal with misalignment of the masks (i.e., gate contact margins).
FIG. 29 is a partial sectional view showing an example of a conventional insulated gate semiconductor device which is described in U.S. Pat. No. 5,034,785. The intervals between cells are shorter in the illustrative device since the illustrative device does not use the gate contact margins which are used in the conventional technique of FIG. 28.
The device shown in FIG. 29 is a DMOS power transistor, and includes a gate of a trench structure. The gate electrodes 7 have a surface which is recessed from the first major surface 14 of the semiconductor substrate 13. Denoted at 16 is a source electrode.
In the illustrative structure, the surfaces of the gate electrodes 7 are recessed from the first major surface 14 of the semiconductor substrate 13. This makes a mask unneeded to form the gate electrodes 7 and makes it unnecessary for the source electrode to have a margin for alignment of the masks. Hence, it is possible to reduce the trench pitch.
However, it is necessary to form the N.sup.+ source region 16 deeper than the surfaces of the gate electrodes 7. The N.sup.+ source region 16 therefore tends to be deeper. Since the N.sup.+ source region 16 is formed by diffusion in most cases, when the N.sup.+ source region 16 is diffused deep, the N.sup.+ source region 16 is diffused wide. This increases the trench pitch.
FIG. 30 is a schematic diagram showing side diffusion in the conventional structure. The illustrative device is an IGBT.
In FIG. 30, to ensure that the surfaces of the gate electrodes 7 are recessed from the surfaces of the N.sup.+ emitter regions 4, the N.sup.+ emitter regions 4 are formed deeper and therefore side diffusion of the N.sup.+ emitter regions 4 is large. Hence, to make an exposed surface of the P base layer 3 and the surfaces of the N.sup.+ emitter regions 4 contact each other at the emitter electrode 10, the trench pitch must be formed large. This allows the parasitic transistor to easily turn on.
Another value which is related to the SOA of an element is saturation current I.sub.C (sat).
The value of a current which flows in an IGBT in response to a certain applied gate voltage is expressed as I.sub.C (sat). If the value I.sub.C (sat) is too large, the parasitic transistor easily turns on, which in turn destroys the IGBT.